`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   17:25:12 10/27/2008
// Design Name:   RegisterFile
// Module Name:   C:/3710/RegisterFile_tb.v
// Project Name:  CR16
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: RegisterFile
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module RegisterFile_tb;

	// Inputs
	reg clk;
	reg regwrite;
	reg [3:0] readAddress;
	reg [3:0] readWriteAddress;
	reg [15:0] writeData;

	// Outputs
	wire [15:0] readData;
	wire [15:0] readWriteData;
	
	// Variables for testbench
	integer i = 0;
	integer VERBOSE = 1; // Change to 1 to see verbose testbench output

	// Instantiate the Unit Under Test (UUT)
	RegisterFile uut (
		.clk(clk), 
		.regwrite(regwrite), 
		.readAddress(readAddress), 
		.readWriteAddress(readWriteAddress), 
		.writeData(writeData), 
		.readData(readData), 
		.readWriteData(readWriteData)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		regwrite = 0;
		readAddress = 0;
		readWriteAddress = 0;
		writeData = 0;
		#100
	
	for( i = 0; i < 1000; i = i+1)
	begin
		#5
		clk = ~clk;
		if(i == 5)
		begin
		regwrite = 1;
		readWriteAddress = 0;
		writeData = 16'd256;
		end
		if(i == 10)
		begin
		readWriteAddress = 4'd10;
		readAddress = 4'd10;
		end
	end
	
	end
      
endmodule

